CMOS circuits are used in a variety of integrated circuit (IC) applications. A CMOS process can be used to fabricate many different sorts of functionality, such as memory, logic, and switching, and thus CMOS techniques are particularly desirable in applications where an IC includes several different types of functional blocks.
One family of ICs employing CMOS fabrication techniques are programmable logic devices (PLDs). PLDs are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
PLDs and other ICs that are specialized to be radiation tolerant are desirable for certain applications. Such ICs are often referred to as single event upset (SEU) tolerant ICs, heavy ion tolerant (HIT) ICs or radiation-hardened ICs. An SEU arises when a heavy ion or high-energy particle, such as an alpha particle or neutron, hits a memory cell, charging internal nodes of the memory cell that can change the memory state. For convenience of discussion, an SEU will be referred to as an “ion hit,” whether it involves an ion or other high-energy particle causing the error.
Two basic approaches to improve SEU tolerance have been tried. One approach is commonly called “resistive hardening;” however, resistive hardening can significantly degrade latch performance. Another disadvantage arises if a standard CMOS fabrication has to be modified to accommodate a resistively hardened IC. It is highly desirable that SEU tolerant ICs be made using standard CMOS fabrication processes.
Another approach to improve SEU tolerance is commonly called “design hardening.” Design hardening generally refers to laying out a memory cell or other circuit to improve recovery of data after ion hits. A general discussion of design hardening is found in the paper entitled Two CMOS Memory Cells Suitable for the Design of SEU-Tolerant VLSI Circuits, by Bessot et al., IEEE Transactions on Nuclear Science, Vol. 41, No. 6 (December 1994).
In design hardening, basically redundant storage bits are located in two different places, maintaining a source of uncorrupted data after an SEU corrupts one of the storage bits. Many variations are known, using sixteen-, fourteen- and twelve-transistor HIT memory cells.
FIG. 1A is a circuit diagram of a prior-art twelve-transistor memory cell 100. Output nodes QA, QB are initially at “1” and “0” states, respectively. In normal operation, a low (inactive) read/write signal RW conserves the logical states of the output nodes QA, QB. During a read operation, VDD data lines 102, 104 are precharged. Output QA will remain high as the read/write signal RW goes high because output QA is connected to the data line 102 through transistors 106, 108. Output QB will remain low because transistors 110, 112 are both one, discharging data line 104.
Providing new data values on data lines 102, 104 (i.e. data values “0” and “1”, respectively), while the read/write signal RW goes high changes the state of the memory cell 100. In this condition, transistor 114 will push node 116 high, turning transistor 118 OFF and transistor 106 ON. Since transistor 120 is OFF, output QA is coupled to data line 102, forcing the value at output QA to “0.” Transistor 112 is turned OFF, coupling output QB to data line 104. Output QB is forced to “1,” which turns transistor 120 ON and turns transistor 114 OFF. Thus, output QA asserts a “0” value, and node 118 presents a high impedance.
From the initial state of the memory cell 100 (i.e. QA=1, QB=0), output nodes QA, QB and node 116 are sensitive to SEU. For example, if a high-energy particle, represented by arrow 107, strikes the drain of transistor 106, output node QA will go low. Transistor 112 will turn OFF, and transistor 122 will turn ON. Then, output node QB is not biased, but will conserve its “0” state by capacitive effect. Transistors 122 and 124 are both ON, but the gate width of transistor 122 is designed to be longer than the gate width of transistor 124; thus, node 126 will remain at 1. Transistor 118 is still ON, and output node QA is restored to “1,” recovering the upset.
If a high-energy particle, represented by arrow 127, strikes the drain of transistor 128, output node QB will go to “1,” turning transistor 120 ON and turning transistor 114 OFF. Node 116 goes to a high impedance, conserving its “0” state. Transistors 130, 112 are still ON, and output node QB is restored to its initial state of “0.”
If a high-energy particle, represented by arrow 131, hits the drain of transistor 132, node 116 will go high, turning transistor 106 ON and turning transistor 118 OFF. As transistor 120 and transistor 124 are OFF, output node 116 and node 126 become high-impedance nodes, which conserves their data states. Output node QB is still low, and transistor 114 will remain ON, restoring the state of node 116.
However, the contents of the memory cell 100 can be corrupted by a high-energy particle strike that affects more than one node. For example, a particle strike at node 116 results in transistors 118, 124 turning OFF. If that same particle also strikes output node QA, transistor 112 turns OFF and transistor 122 turns ON. Node 126 is pulled down, turning transistor 128 ON, and turning transistor 130 OFF. Then, output node QB goes high, turning transistor 120 ON and turning transistor 124 OFF. Node 116 is asserted to “1” and output node QA is asserted to “0,” thus the contents (i.e. memory state(s)) of the memory cell 100 are corrupted. In similar fashion, a particle strike on output nodes QB and 116 can corrupt data in the memory cell 100.
FIG. 1B is a circuit diagram of another prior-art twelve-transistor memory cell 150. The operation of the memory cell 150 will be familiar to those of skill in the art, and a detailed description of its operation is therefore omitted. However, the memory cell 150 can also be corrupted by a particle strike that affects multiple nodes.
Therefore, memory that is more tolerant to an SEU strike affecting multiple nodes is desirable.